The invention relates generally to computer semiconductor memory cards based on dynamic random access memory (DRAM) devices and which consequently involve DRAM refresh operations, and in particular this invention relates to devices and methods that provide for refreshing of the DRAM devices on plug-in boards in an automatic way that is self-contained on the memory card and optimum for whatever type of DRAM devices are being used.
The use of DRAMs for main memory and for expansion board memory is conventional in personal computer systems. The fact that DRAM-type memories need outside stimulus to "refresh" their individual memory cells periodically is well-known to those skilled in the art. See, "DRAM Refresh Modes," Motorola Semiconductor Application Note AN987, Motorola Memory Data, rev. 6, 1990, pp.13-2 to 13-3. DRAMs have also traditionally only been offered in 16, 18, or 20-pin DIP packages and do not have enough pins to directly address the million or so bits of information inside. So the addresses have been traditionally multiplexed onto an address bus to reduce the number of address pins in the order of 50%. The outside interface to the DRAM must then split system addresses in half and send then along the same bus. Half those addresses are strobed into DRAM registers with a "RAS" signal and the other half with a "CAS" signal. The RAS and CAS must be generated by the DRAM interface circuitry. But even though external DRAM interface and refresh circuitry typically adds cost and inserts refresh cycles that can interfere with and slow down system access, DRAM memories nevertheless compare very favorably with other types of devices on many different scores.
FIG. 10 illustrates a common prior art interfacing of a computer with DRAM. A central processing unit (CPU) 100 sends a plurality of signals to a DRAM interface 101 which, in turn, modifies these signals and applies them to DRAM 102. The CPU 100 signals include address 100a, read control (RD) 100b, write control (WR) 100c, memory request (MRQ) 100d, and refresh control (RFSH) 100e. Databus 100f exchanges data bidirectionally and directly between CPU 100 and DRAM 102. CPU 100 must issue periodic DRAM refresh cycles so that data at addresses within DRAM 102 do not spoil. Normal data transfers are suspended during such refresh cycles. The required period of refresh cycles depends on the actual type of DRAM device being employed in DRAM 102.
DRAM interface 101 provides row address strobe (RAS) 101a, column address strobe (CAS) 10lb, and multiplexed addresses 101c, 101d, and 101e. DRAM interface circuit 101 outputs RAS 101a, CAS 10lb and address signals 101c, 101d and 101e, based on the particular states of address 100a and control signals RD 100b, WR 100c, and MRQ 100d. (The control signals are all low true, as is the custom in such designs, but the signal names are not shown as RD, WR, MRQ, etc., for the sake of simplicity.) During refresh operations, RAS 101a, CAS 10lb and addresses 101c, 101d and 101e are periodically output in a sequence to DRAM 102 to retain data stored in the DRAM 102. (DRAM memory cells will be refreshed if simply addressed.)
FIG. 11 shows a generalized timing that is applicable to the circuit of FIG. 10. To access DRAM 102, CPU outputs address 100a, MRQ 100d goes low, and either RD 100b or WR 100c go low. DRAM interface circuit 101 multiplexes the original address onto addresses 101c, 101d and 101e, and coordinates RAS 101a and CAS 10lb to indicate to DRAM 102 whether the address lines currently have the row or the column half of the complete address. (Note how the negative going edges of RAS 101a and CAS 10lb are skewed slightly in time.) Data is exchanged between CPU 100 (data to DRAM 102 if a write, data from DRAM 102 if a read cycle) over databus 100f with addresses in DRAM 102. A refresh generator (e.g., a software program) is built into CPU 100 that outputs refresh signal (RFSH) 100e to DRAM interface circuit 101, along with an appropriate address signal 100a and MRQ 100d. DRAM interface circuit 101 outputs RAS 101a, CAS 10l b, and address 101c, 101d and 101e in order to refresh DRAM 102 and thereby retain the data stored at the various addresses in DRAM 102. The refresh operation need not be output by the CPU at completely arbitrary times. It is often preferable to output a refresh cycle at prescribed times, such as after fetching an instruction from memory.
Memory cards are a convenient way for users to add more memory to computer systems. Such cards can be plugged into sockets universally provided standard on most popular systems. Some of these prior art memory cards do not initiate their own refresh cycles. Such memory cards include only the equivalent function of DRAM 102. The individual timing of refresh signals often differs, depending on the CPU being used. For practical reasons, no CPU can always supply an optimum refresh signal to every kind of DRAM-equipped memory card, because the needs of the DRAMs themselves differ, especially when comparing larger and smaller DRAMs. Common refresh periods are 8, 16, 32, and 64 milliseconds. So if any of these four could be used, a prior art memory card would have to refresh every eight milliseconds to ensure that the memory is properly refreshed. Other prior art systems always follow a read or write operation by a refresh operation, as a result, the overall access time of the memory card is stretched out.
A memory card is needed that can automatically refresh itself with an optimum refresh period, and one able to separate data transfers from refresh operations. Such a memory card would shorten access times and improve interoperability and reliability.